library verilog;
use verilog.vl_types.all;
entity SRAM is
    port(
        ce_r            : in     vl_logic;
        oe_r            : in     vl_logic;
        rw_r            : in     vl_logic;
        address_r       : in     vl_logic_vector(3 downto 0);
        data_out_r      : inout  vl_logic_vector(7 downto 0);
        ce_l            : in     vl_logic;
        oe_l            : in     vl_logic;
        rw_l            : in     vl_logic;
        address_l       : in     vl_logic_vector(3 downto 0);
        data_out_l      : inout  vl_logic_vector(7 downto 0)
    );
end SRAM;
